The original MK14 has a double sided 32-way edge connector for expansion. Only the top side is connected (designated B), the bottom side (designated A) is used for connection to the VDU board however the required signals have to be hardwired across the board !
The following table shows the signal allocations from the original MK14 schematics (Side B only):
| Pin No. | Signal | Description |
| 1 | +5V | Power +5V |
| 2 | +5V | |
| 3 | +5V | |
| 4 | 0V | Power 0V |
| 5 | 0V | |
| 6 | 0V | |
| 7 | 0V/NADS | 0V on early Issue PCBs and NADS on later issues |
| 8 | NADS | Address Strobe, when low indicates status and upper four address lines are on data bus |
| 9 | PB6 | 8154 Port B |
| 10 | PB5 | |
| 11 | PB7 | |
| 12 | PB4 | |
| 13 | PB3 | |
| 14 | PB2 | |
| 15 | PB1 | |
| 16 | PB0 | |
| 17 | PA7 | 8154 Port A |
| 18 | INTR | Interrupt from 8154 |
| 19 | PA6 | 8154 Port A |
| 20 | PA0 | |
| 21 | PA5 | |
| 22 | PA1 | |
| 23 | PA4 | |
| 24 | PA2 | |
| 25 | PA3 | |
| 26 | SENSEA | Sense A condition input to processor can also be used as interrupt input |
| 27 | SIN | Serial Input to processor E-register |
| 28 | SENSEB | Sense B condition input to processor, |
| 29 | SOUT | Serial Output from processor E-register |
| 30 | FLAG0 | Flag 0 output from processor |
| 31 | FLAG2 | Flag 2 output from processor |
| 32 | FLAG1 | Flag 1 output from processor |
The VDU Board has provision for a 64-way DIN41612 connector rather than an edge connector, the following table shows the signal allocations from the original MK14 VDU schematic:
| Pin No. | Side A Signal |
Description | Side B Signal |
Description |
| 1 | 0V | Power 0V | ||
| 2 | A0 | Lower 12 bits of Address Bus | ||
| 3 | A1 | |||
| 4 | A2 | |||
| 5 | A3 | |||
| 6 | A4 | |||
| 7 | A5 | |||
| 8 | A6 | |||
| 9 | A7 | PS1 | Page Select Lines | |
| 10 | A8 | PS2 | ||
| 11 | A9 | PS3 | ||
| 12 | A10 | PS4 | ||
| 13 | A11 | VDU OFF | VDU on (low) / off (high) | |
| 14 | A12 | Upper four Address allocated but not used | GRAPH/CHAR | Selects between Graphics (high) and Character (low) modes of operation |
| 15 | A13 | REVERSE | Reverse Pages (low for reverse) | |
| 16 | A14 | INVERT | Inverts video output (low for black on white) | |
| 17 | A15 | TOP PAGE | Output that is high during first half of frame | |
| 18 | D0 | Data Bus | ||
| 19 | D1 | |||
| 20 | D2 | |||
| 21 | D3 | |||
| 22 | D4 | |||
| 23 | D5 | |||
| 24 | D6 | |||
| 25 | D7 | |||
| 26 | ||||
| 27 | XOUT | 4MHz clock input | ||
| 28 | NRDS | Read Data Strobe, data read on trailing edge | ||
| 29 | ||||
| 30 | ||||
| 31 | NENIN | Enable Input, when low processor can access bus | ||
| 32 | +5V | Power +5V |